1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly the present invention relates to a method of forming a buried contact.
2. Description of Related Art
SRAM, an acronym for Static Random Access Memory, is one of the fastest operating semiconductor memory devices widely used in computer equipment. An SRAM can be divided into two structural regions, namely, a memory cell region and a peripheral circuit region. The memory cell is used for storing binary data, whereas the peripheral circuit region has a number of address decoders, which are used to decode memory cell addresses issued from the memory cell region as well as to control related memory circuits.
In the past, most SRAM contact window structures were formed above the source/drain region. With the trend toward increased integration density, the conventional contact window structures turn out to be inefficient. Consequently, a buried contact structure suitable for fabricating local interconnects has been introduced. The buried contact structure is capable of reducing area occupation by up to 25%, for example, in SRAM. Hence, buried contact structure is indispensable in the fabrication of high-density electronic products.
In the conventional process of forming a buried contact, the trench can easily punch through the N.sup.- (source/drain) junction. Therefore, the buried contact is in contact with the substrate. The junction thus is cut off and high resistance occurs at the junction.
FIGS. 1A through 1F are cross-sectional views of a portion of a semiconductor device showing the conventional process of fabricating a buried contact.
In FIG. 1A, a shallow trench isolation structure (STI) 102 is formed in a semiconductor substrate 100. A patterned gate oxide layer 104 and a first patterned polysilicon layer 106 are formed in sequence over the substrate 100. An N.sup.+ ion implantation is performed to form a N.sup.+ junction 108 in the substrate 100.
In FIG. 1B, a second polysilicon layer 110 and silicide layer 112 are formed over the substrate 100.
In FIG. 1C, the silicide layer 112, the first polysilicon layer 110, and a second polysilicon layer 106 are patterned to form a gate 114 and a buried contact 116. The buried contact 116 is electrically coupled with the N.sup.+ junction 108. A trench 118, which punches through the N.sup.+ junction 108 and exposes the substrate 100, is often formed.
In FIG. 1D, an N.sup.- ion implantation is performed to form an N.sup.- junction 120 in the substrate 100. Because the trench 118 punches through the N.sup.+ junction 108, the N.sup.- junction 112 simultaneously forms below the trench 118.
In FIG. 1E, spacer layer 124 are formed on the substrate 100. Due to the existence of the trench 118, spacer layers 124 are also formed in the trench 118.
In FIG. 1F, an N.sup.- ion implantation is performed. An N.sup.+ junction 126 is formed in the substrate 100. The N.sup.+ junction 126 is located between the N.sup.+ junction 108 and the N.sup.- junction 120. In the conventional process, the spacer layer 124 is formed in the trench 118 (FIG. 1D). Trench 118 punches through the N.sup.+ junction 108 and high resistance thus occurs.
In the conventional process of forming a buried contact, the trench easily punches through the N.sup.+ (source/drain) junction. Therefore, the buried contact is in contact with the substrate. The junction thus is cut off. In cases where the trench does not completely punch through the N.sup.+ (source/drain) junction, high resistance at the junction still occurs.